1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a latch circuit and a method of preventing a semiconductor integrated circuit from malfunctioning.
2. Description of Related Art
In some case, radioactive rays penetrate a semiconductor integrated circuit. Alpha rays, neutron rays and the like are conceivable as such radioactive rays. In some case, alpha rays are generated when a radioactive isotope contained in a semiconductor integrated circuit package or wiring. Neutron rays derive from cosmic rays. In some case, electrical noise is generated in a semiconductor circuit by a radioactive ray to cause a malfunction. A malfunction due to a radioactive ray is called a soft error in contrast with a hard error due to a fixed fault.
In general, a soft error is a temporary malfunction. For example, in the case of a latch circuit included in a semiconductor integrated circuit, a variation in voltage at a storage node is insignificantly small if the charge capacity of the storage node is sufficiently large. In recent years, however, the miniaturization of semiconductor integrated circuits has advanced. With this, the charge capacity of a latch circuit at a storage node has been reduced. As a result, the logical level of latched data can be easily inverted by the generation of electrical noise. That is, in recent years, a malfunction due to a radioactive ray in a latch circuit included in a semiconductor integrated circuit can become a fixed error.
Non-Patent Document 1 describes a technique to improve the soft-error tolerance of a latch circuit. FIG. 1 is a circuit diagram showing a latch circuit described in non-patent document 1. In this latch circuit, an input signal from an input end IN is latched when a clock signal CK is high level. When the clock signal CK is low level, the input signal input from the input end IN is directly output from an output end OUT. That is, the latch circuit is in a pass-through state when the clock signal CK is low level. In this latch circuit, a capacitor is connected through a transfer gate A to the output end OUT, which also serves as a storage node. At the time of latching, the transfer gate A is made conductive to electrically connect the capacitor to the output end OUT. As a result, the charge capacity at the storage node of the output end OUT is increased. By the increase in charge capacity, variation in voltage at the storage node is made insignificantly small even when electrical noise occurs due to a radioactive ray, thus enabling latched data to be correctly maintained. At the time of pass-through, the capacitor is electrically isolated from the storage node (output end OUT). Therefore no delay of the rate of transfer of data occurs at the time of pass-through. The soft-error tolerance of the latch circuit is thus improved while maintaining high-speed operation.
[Non-Patent Document 1] T. Karnik, et al, “Selective node engineering for chip-level soft error rate improvement”, 2002 Symposium on VLSI Circuits, Digest of Technical Papers, June 2002, pp. 204-205
Patent Document 1 (Japanese Patent Laid-Open No. 2006-65919) and patent document 2 (Japanese Patent Laid-Open No. 2008-52847) also describe other techniques as measures against soft errors.
Patent Document 1 discloses a memory circuit including a latch circuit, and a ferroelectric capacitor connected to the latch circuit via a transfer gate. Regarding the technology of Document 1, when writing a data to the latch circuit, at that time a voltage potential corresponding a node of the latch circuit is held at one electrode of the capacitor and the complementary voltage potential corresponding the other node of the latch circuit is maintained at the other electrode of the capacitor.
Patent Document 2 discloses a latch circuit, with two capacitors each connected to the latch circuit via switching elements. The Document 2 further discloses inverters each of which connects the respective capacitor with the respective nodes of the latch circuit without intervening the switching elements. Based on the driving condition, this technology can enlarge the capacitance of the latch circuit.